Developed (white-box) requirements for various generations of Infinera ASICs in
these areas: G.709 OTN tributary interfaces, FlexE, FlexO, Infinera Proprietary
Signals/Formats (used on the line-side interfaces), Overhead processing, Alarm
Propagation. Supported the ASIC development team through all stages of
development to ensure full compliance to applicable standards.
Developed requirements for Layer 1 encryption (AES-GCM, AES-CTR modes) in INFN
ASICs: at the ODU layer (in mapper ASIC) & bulk encryption (DSP ASIC). These
requirements addressed the following aspects: algorithmic compliance, support
for minimizing the cryptographic boundary (for FIPS 140-2 validation).
Specified the architecture for supporting protection switching schemes (e.g.,
1+1 SNCP, Y-cable) in Infinera transponders and muxponders. This involved the
timely reporting of defects to the protection FSMs, FPGA assist to minimize the
switching time.
Developed requirements for FEC Support for OC3/1GE Optical Supervisory Channels
Developed the End-2-End mechanism for Shared Mesh Protection (SMP) for ODU
connections. This mechanism has been presented in various contributions to
ITU-T SG15 Q9 (OTN Equipment). This work contributed to the ITU-T
recommendation G.783.3.
Defined the mechanism to support hitless ODUFlex resizing (specific to DTN-X
networks). Working with ASIC & Software teams to get the mechanism implemented.
Developed requirements related to control channel realization (e.g. trib & line
side GCC channels) for several generations of Infinera Network Elements.
Developed DTN-X Network Architecture Specification. This specification takes a
top-down view of DTN-X networks, and contains an in-depth coverage of these
aspects: Layers (i.e. Signals, Formats), Adaptations, OTN atomic function
realization, and Defect propagation. This document is used as the basis to
derive requirements for the ASICs/FPGAs.
Developed DTN Network Element requirements for these areas: GMPLS, L1VPN,
Datapath recovery (protection, and restoration).
System Architect
Fujitsu Network Communications
Participated in the architecture definition of the FW9500 hybrid platform that
supported TDM & Packet services (e.g. Point-to-Point Ethernet, VPLS) based on
MPLS Pseudowires
Developed System Level Requirements for VPLS/H-VPLS, Control Plane High-
Availability.
Contractor (SW development)
Nortel
RSVP-TE for GGSN node: Wrote Functional Spec, Detailed Design & Designer Test
plan. Worked on design changes support for a redundant control processor.
BGP/MPLS VPNs for GGSN node: Wrote the Designer Test plan, Added support for
MPLS & VRF historical statistics.
Contractor (SW development)
Avici
Resolved software issues related to: PPP, SONET Link Aggregation, MPLS LSP
Protection (Fast Reroute).
Contractor (Systems Arch)
Ciena
Specified the functional requirements for the CoreDirector features: Connection
Test Access, Connection Loopback, OSI/DCC, 1GE/10GE tunneling with SONET/SDH
VCAT/LCAS).
Systems Architect
Fujitsu Network Communications
Part of the team tasked with developing the architecture for the first
TDM/Packet Hybrid. Primarily responsible for Layer 2 and Layer 3 VPN support
over MPLS networks.
Investigated protection of Point-to-Multipoint (P2MP, or multicast) MPLS LSPs,
for the purposes of offering a fully protected TLS service.
Specified the optical UNI (O-UNI) interface between an MPLS LER (Label Edge
Router), and the Optical Network Element (ONE).
Specification of Network Element Management Information models, and protocol
specific realizations (in terms of TL-1 and SNMP)
Member of Scientific Staff
Nortel
Part of a team defining the End-to-end architecture of a system offering
Broadband access.
Developed various features for the HFC Cable Modem. E.g. Lightweight ATM
signaling protocol, IP NAT (to support multiple attached PCs), Software Upgrade
Designed & Developed software for the following layers in the OSI Stack: LAPD
(with QoS), Layer 3 (CLNP, IS-IS, ES-IS), and Layer 5 (Session Layer).
Implemented performance enhancements at Layers 2 through 4 of the OSI stack
Implemented various STREAMs modules (e.g. TPI, Line Discipline Module, Serial
Drivers)
Implemented a bridge for interconnecting IBM Token Ring LANs via a Frame Relay
WAN
Analysis, Design, and Implementation of transparent access to (XMS based)
remote file servers (via X.25 networks), file transfer utilities.
SW Designer
Micom
Designed and Implemented software for data communication protocols (e.g.
BISYNC, SDLC, ISO Transport Layer 4/0, Session/Transport layers for Teletext
service)
Education
Ph.D. (Electrical Engineering)
Carleton University
Thesis: Learning Algorithms for Data Storage & Retrieval
Supervisor: Prof. B. John Oommen
M. Sc. (Computer Science)
McGill University
Thesis: A Communications Controller for Small-Computer Networks
Supervisor: Prof. Kasi Ananthanarayanan
B. Tech. (Electronics and Electrical Communication)
Indian Institute of Technology
Undergraduate Project: Symbolic Circuit Analysis
Awards
Infinera Spectrum Award
Infinera CEO ∙
September 2024
Part of the team that solved a 400GE interop issue between customer network router & INFN muxponder
Infinera President’s Award
Infinera President ∙
May 2009
Carleton University Medal for Outstanding Graduate Work at the Ph.D. level
Carleton University ∙
May 1991
Awarded the best thesis of the year
Post-Graduate Scholarship from Nortel
Nortel ∙
September 1987
Awarded for the duration of the Ph.D. program
Post-Graduate Scholarship from the Natural Sciences and Engineering Research Council (NSERC) of Canada
NSERC ∙
September 1987
Awarded for the duration of the Ph.D. program
President of India silver medal
IIT Kharagpur ∙
May 1978
Awarded for best academic performance in the graduating batch of the B. Tech program in the Electronics & Communication Engineering (ECE) department
Stood fourth in the state of West Bengal in Higher Secondary Examination
West Bengal HS Board ∙
June 1973
The state recognizes the top ten students who appeared for the Higher Secondary Board Examination every year.