About Me

I am a system architect in the hardware architecture group at Infinera Corp. In this role, I have been responsible for the OTN features (e.g. client mappings, ODU multiplexing, protection switching) in several INFN product families (e.g. DTN, DTN-X, XT, GX). This activity involves examining the end-to-end services in a top-down fashion, starting at the network level, and then using this high-level view to derive requirements for (a) the Network Element as a whole, and (b) the datapath ASICs/FPGAs that implement these features. In deriving these requirements, I have used the standards/recommendations developed by ITU-T/IEEE as guidance, and then expanded on these to generate detailed guidance for ASIC/FPGA designers. As part of this activity, I have tracked & contributed to ITU-T SG15 Q11 activities related to OTN Signals/Formats/Equipment.

I have developed requirements to support Layer 1 encryption services in all the INFN datapath ASICs, and DSPs. This activity too, involved a top-down examination of the end-to-end view of encrypted services (e.g. datapath AES encryption, overheads, key exchange, key switches etc.), and then determining the functions/aspects which will be implemented by the ASICs.

I have had extensive experience with the development of SONET networks and network elements, as well as Packet Optical Network elements that support both TDM, and packet services. I started my career developing software for various protocol stacks (e.g. X.21, X.75, HDLC/BiSync, OSI Layers 2-5), and then gradually migrated to roles that define architecture for products/components.

My graduate work was in the area of adaptive data structures. This work, builds on the concepts from Learning Automata, and examines the effectiveness of heuristics (e.g. Move-to-Front, Transpose) which organize data structures with each access, so as to (hopefully) optimize future accesses.